1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Description of Related Art
An electronic device such as a computer typically includes a data storing means storing data. One of semiconductor storage devices employed as the data storing means includes an SRAM (Static Random Access Memory). The SRAM has the advantage of high-speed operation that there is no need to perform a refresh operation and that the memory cell access time is short and so on.
However, transistors forming the SRAM cell have been miniaturized in recent years and the current driving ability of the transistor has been decreasing, which interrupts the high-speed operation. In order to facilitate the data reading operation of the memory cell, there has been proposed an SRAM driving bit lines by a read-only transistor having high driving ability. One example of the SRAM including the read-only transistor is disclosed in Japanese Unexamined Patent Application Publication No. 2006-59520.
FIG. 9 shows a circuit diagram of an SRAM cell 11 disclosed in Japanese Unexamined Patent Application Publication No. 2006-59520. As shown in FIG. 9, the SRAM cell 11 includes an inverter having an nMOS transistor Tr10 and a pMOS transistor Tr20 and an inverter having an nMOS transistor Tr11 and a pMOS transistor Tr21 so as to form a latch circuit. Further, inputs and outputs of each inverter are connected at a node A1 and a node B1. An nMOS transistor Tr30 is connected between the node A1 and a bit line DT. A gate of the nMOS transistor Tr30 is connected to a word line WL1. An nMOS transistor Tr31 is connected between the node B1 and a bit line DB. A gate of the nMOS transistor Tr31 is connected to the word line WL1.
Further, an nMOS transistor Tr40 is connected between the bit line DT and a node C1. A gate of the nMOS transistor Tr40 is connected to the word line WL1. An nMOS transistor Tr50 is connected between the node C1 and a ground terminal (Vss). A gate of the nMOS transistor Tr50 is connected to the node B1. Note that the bit line DT functions both as a reading port and as a writing port. As shown in FIG. 10, the SRAM circuit 10 has a configuration in which a plurality of memory cells having a similar configuration as that of the SRAM cell 11 are connected to one bit line pair.
When low-level data is stored in the node A1 and high-level data is stored in the node B1, the SRAM cell 11 sets the bit line DT to the low level and sets the bit line DB to the high level in reading the data. In a precharge period before the data reading is started, both of the bit lines DT and DB are set to the high level. When the data is read out from the SRAM cell 11 with such a condition, the SRAM cell 11 is able to draw current rapidly from the bit line DT by the nMOS transistor Tr40. Accordingly, the SRAM cell 11 realizes the high-speed operation while operating with low power supply voltage. Note that the current driving ability of the nMOS transistor Tr40 is set high in order to realize the high-speed operation.
However, the nMOS transistor Tr40 has a large channel leak current as well. Therefore, there is caused a potential fluctuation of the bit lines due to the channel leak current, which causes data reading failure in the SRAM cell 11. FIG. 11 shows a timing chart showing the operation of the SRAM circuit 10 shown in FIG. 10 for the purpose of describing the problem.
As shown in FIG. 11, the SRAM circuit 10 reads out data during a reading period (Read period in FIG. 11) at the timing t1 to t2. In the example shown in FIG. 11, the word line WL1 is in the high level, and the word lines WL2 and WL3 are in the low level in the reading period. Therefore, the SRAM cell 11 is in a selection state and the SRAM cells 12 and 13 are in a non-selection state. The data is read out from the SRAM cell 11 so that the bit line DT keeps the high level and the bit line DB is in the low level.
At this time, since the word lines WL2 and WL3 are in the low level in the SRAM cells 12 and 13, the nMOS transistor Tr40 is in a disconnection state. On the other hand, the nMOS transistor Tr50 is in a conduction state in accordance with the data stored in the SRAM cells 12 and 13. Accordingly, the nodes C2 and C3 have a ground potential. In summary, a potential difference in accordance with the power supply potential is generated between a source and a drain of the nMOS transistor Tr40 of the SRAM cells 12 and 13.
The nMOS transistor Tr40 used for reading the data has a high current driving ability and a large channel leak current. Therefore, when there is generated a potential difference between the source and the drain of the nMOS transistor Tr40, the leak current flows between the source and the drain of the nMOS transistor Tr40. This leak current flows from the bit line DT in the high impedance state keeping the high level to the ground terminal Vss. Accordingly, the charge is drawn out from the bit line DT due to this leak current, which decreases the potential level of the bit line DT.
In recent years, an operation power supply voltage of the semiconductor storage device has been reduced, and the potential difference between the high level and the low level in the bit line has also been reduced. Therefore, when the potential of the high level reduces in the bit line, a sense amplifier may falsely detect the potential difference of the bit line pair, which causes the data reading failure. Further, since the channel leak current tends to be increased in a high temperature environment, this problem is more significant in the high temperature environment.
Further, Japanese Unexamined Patent Application Publication No. 2004-288306 discloses a technique including a memory cell storing data, a reference cell generating a leak current, and a correction circuit correcting a signal of a bit line in accordance with the leak current from the reference cell. However, since the reference cell and the correction circuit and the like need to be added in this technique, the circuit size is increased.
As stated above, in a semiconductor storage device including a transistor for reading port facilitating a reading operation in a bit line, undesired voltage decrease may occur in the bit line in the reading operation due to the leak current from the transistor facilitating the reading operation, which may cause a reading error.